1. Field of the Invention
This invention relates generally to non-volatile semiconductor memory devices and more particularly to a ferroelectric memory device in which a ferroelectric material is used.
2. Description of the Related Art
The capacitance of a capacitor formed of a ferroelectric material (hereinafter referred to as xe2x80x9cferroelectric capacitancexe2x80x9d) exhibits hysteresis in the relation between an applied voltage and its polarization. A ferroelectric memory device which utilizes ferroelectric capacitors in its memory cells can retain data which have been written in the ferroelectric capacitors by applying voltages thereto by virtue of their residual polarizations even after the applied voltages become zero. Therefore, a non-volatile ferroelectric memory device can be constructed utilizing such characteristics.
During a reading operation in a ferroelectric memory device, stored data is reproduced by applying a voltage to a ferroelectric capacitor to cause a bit-line voltage, which corresponds to zeros or ones of the data stored in the data cell, to develop and then reading the bit-line differential voltage thus developed in accordance with the polarization direction by a sense amplifier. In order to carry out a correct reading operation with such a structure, it is important to make arrange for the difference between the bit-line differential voltage appearing when xe2x80x9c0xe2x80x9d is read and that appearing when xe2x80x9c1xe2x80x9d is read to be sufficiently large.
It is also important for stable reading operations to design the device so that a voltage applied during a writing operation is set to such a value that the polarization of the ferroelectric material is surely reversed.
There has been proposed, for example, in Japanese Unexamined Patent Application, First Publication No. 9-7376, a ferroelectric memory device which is controlled in such a way that a sufficiently large voltage is applied to the ferroelectrics during reading to obtain a sufficient difference between the bit-line differential voltages for reading xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, particularly for low-voltage operation of the device. This conventional control method and the structure of the device will now be described with reference to FIGS. 8 to 10.
In this conventional control method the pre-charge voltage of the bit lines is set, for the stable reading operation of the device, to a value which is higher than that of the supply voltage for the sense amplifiers and the peripheral circuits of the device.
In the case of a memory device where the pre-charge voltage for the bit lines is not stepped up, the voltage applied to the ferroelectric capacitor during a read operation is determined by the charge-sharing between the ferroelectric capacitance and the parasitic capacitance of the bit lines and is therefore lower than that applied thereto during a write operation. As a result, the read operation will not be stable.
In the ferroelectric memory device disclosed in Japanese Unexamined Patent Application, First Publication No. 9-7376, in order to realize a stable reading operation the pre-charge voltage applied during reading is selected to be higher, so that the voltage applied to the ferroelectric capacitance during reading is equivalent to that applied thereto during writing.
FIG. 8 shows the structure of the above conventional ferroelectric memory. As shown in FIG. 8, this memory comprises a step-down power supply circuit 804 provided for reducing the power consumption in a peripheral circuit 802. That is to say, the supply voltage to the peripheral circuit is a stepped-down supply voltage Vcc as obtained by lowering an external supply voltage Vhp fed from the outside.
On the other hand, bit lines BL0 and BL1 are pre-charged with a voltage higher than the stepped-down supply voltage Vcc, for example, with the external supply voltage Vhp fed from the outside. Specifically, a pre-charge circuit 803 is supplied with the external supply voltage Vhp.
FIG. 9 shows the structure of a circuit for the bit-line system of the conventional ferroelectric memory. A memory cell MC1 is comprised of two ferroelectric capacitors (capacitances) FC11 and FC12 and two cell transistors TC11 and TC12. One terminal of the ferroelectric capacitors FC11 and FC12 is connected in common to a plate line PL1 and the other terminal of the ferroelectric capacitors FC11 and FC12 is connected to the sources of the cell transistors TC11 and TC12, respectively. The gates of the cell transistors TC11 and TC12 are connected in common to a word line WL1 and the drains of the cell transistors TC11 and TC12 are connected to the bit lines BL0 and BL1, respectively. Other memory cells (MC2) than the memory cell MC1 have a circuit structure similar to that of the memory cell MC1 and their configuration and element sizes are equivalent to those of MC1.
With the above circuit structure, the potential of the plate line PL1 is fixed to a voltage equal to a half of the stepped-down supply voltage Vcc, i.e., Vcc/2.
A sense amplifier (SA) 801 is of the latch type and is constituted by first and second inverters whose input and output terminals are cross-coupled, wherein the first inverter is comprised of a P-channel MOS transistor PM1 and an N-channel MOS transistor NM1 connected between the terminals for sense-amplifier activation signals SAP and SAN and the second inverter is comprised of a P-channel MOS transistor PM2 and an N-channel MOS transistor NM2 connected between these terminals. The output terminal of the first inverter and the input terminal of the second inverter are connected to the bit line BL0, while the input terminal of the first inverter and the output terminal of the second inverter are connected to the bit line BL1.
P-channel MOS transistors PM3 and PM4, which are connected respectively between the bit lines BL0 and BL1 and a terminal for the supply voltage Vhp and have respective gates supplied with a pre-charge signal PBL, constitute the pre-charge circuit 803 which serves to pre-charge the bit lines when they are turned on.
The output terminals of the sense amplifier (SA) 801 are connected respectively to I/O lines IO0 and IO1 through column switches Y0 and Y1 whose ON/OFF states are controlled by a column selection signal YSW.
FIG. 10 is a time chart for the description of the operation of the circuits of FIG. 9 and shows each waveform of the signals on the word line WL1 and the plate line PL1, the pre-charge signal PBL, the signals on the bit lines BL0 and BL1 and the sense amplifier activation signals SAN and SAP. When the word line WL1 is brought to a high level during a read operation, voltages determined by the ratios of bit-line parasitic capacitances CB0 and CB1 to the capacitances of the ferroelectric capacitors are applied to these ferroelectric capacitors, whereby data is read out.
During a re-writing operation, since the voltage of the plate line PL1 is at Vcc/2, a voltage equal to Vcc/2 is applied across the terminals of each ferroelectric capacitor.
According to this conventional structure, the voltage applied to the ferroelectric capacitors during reading can be made equivalent to that applied thereto during writing by setting the pre-charge voltage of the bit lines to Vhp which is higher than the voltage Vcc for operating the peripheral circuit 802. A stable reading operation of the memory can thus be realized.
In the case where a reading operation is carried out with the voltage of the plate line being at Vcc or at the ground potential, since the voltages applied to the ferroelectrics are sufficient, the pre-charge voltage of the bit lines need not be increased and may be at the ground potential or Vcc.
FIG. 5 shows the hysteresis of the ferroelectrics. In FIG. 5, the abscissa represents the applied voltage and the ordinate represents the polarization (or charge Q). The hysteresis deteriorates in accordance with the fatigue of and the imprint on the ferroelectric film, which depend on the number of accesses to the memory cell, and further in accordance with the increase of the total time of retaining data. More specifically, a ferroelectric film of the memory cell, for which the hysteresis loop has repetitively been reversed, will have a reduced hysteresis loop due to fatigue.
FIG. 6 shows effects of the number of accesses to the ferroelectric capacitor on the bit-line voltage read therefrom due to the fatigue of the ferroelectric film. More specifically, in the case of reading xe2x80x9c1xe2x80x9d which accompanies a reversal of polarization, the read-out bit-line voltage decreases as the number of read operation cycles increases. In contrast, in the case of reading xe2x80x9c0xe2x80x9d which is an operation without a reversal of polarization, the read-out bit-line voltage does not much depend on the number of reading operation cycles and is substantially constant.
The ferroelectric memory disclosed in Japanese Unexamined Patent Application, First Publication No. 9-7376 and described above with reference to FIGS. 8 to 10 has the following problems.
A first problem is that the permitted number of operation cycles of the memory cell with ferroelectric capacitors will be decreased.
The reason for this is that no consideration has been given to the fact that the particular deterioration of characteristics such as the fatigue of the ferroelectric film and the imprinting depends on the applied voltage.
In general, the voltage applied to the ferroelectrics through a read/write cycle will be at a maximum when a write operation is performed. Thus, the voltage applied during a write operation will determine the permitted number of operation cycles of the ferroelectric capacitor. As will later be described, as the applied voltage is lowered the permitted number of operation cycles will increase, but the write operation will not be carried out correctly when the applied voltage is below the coercive voltage.
Thus, in the above-described conventional ferroelectric memory in which the pre-charge voltage is increased during reading, the pre-charge voltage Vhp of the bit-lines is always higher than the minimum write voltage and cannot be lower than that.
In addition, since a voltage equivalent to that applied during writing is applied to the ferroelectrics during reading, the allowable number of operation cycles is decreased due to fatigue and imprinting.
Furthermore, because of the necessity of increasing the bit-line pre-charge voltage, the effect of reducing the internal power consumption by the step-down power supply circuit is low.
A second problem is that the bit-line capacitances have not been optimized with respect to the characteristics of the ferroelectric capacitors.
The reason for this is that no consideration has been given to the fact that the signal voltage on the bit lines is determined by the relation between the capacitance of the ferroelectric capacitors and that of the bit lines. More specifically, a sufficient signal voltage can be obtained, without raising the bit-line pre-charge voltage, by selecting the optimum bit-line capacitance in accordance with the number of memory cells connected to the bit line.
When considering a stable operation which may be obtained by taking into consideration the deterioration of characteristics specific to the ferroelectrics such as the fatigue and imprinting, a stable read operation cannot be expected from the above-described conventional method. The conventional method rather leads to deterioration of the characteristics of the ferroelectrics and lowers the reliability due to its increased pre-charge voltage.
It is therefore an object of the present invention to provide a semiconductor memory device constructed using a ferroelectric material in which the permitted number of operation cycles is increased by solving the aforesaid first problem.
It is another object of the present invention to provide a ferroelectric memory device constructed using a ferroelectric material in which the permitted number of operation cycles is increased by solving the aforesaid second problem.
It is a further object of the present invention to provide a ferroelectric memory device having a read circuit of high reliability by solving the aforesaid first and second problems.
To achieve the above objects, a ferroelectric memory device according to the present invention comprises a memory cell array which comprises a plurality of memory cells arranged in rows and columns, each memory cell including a capacitor element formed by first and second capacitor electrodes with a ferroelectric film sandwiched therebetween for storing information in accordance with polarization states of said ferroelectric film and a transistor having a source and a drain, one of which is connected to one of the first and second capacitor electrodes of said capacitor element; a plurality of word lines provided for each row of the memory cell array and connected to gate of each transistor of memory cells included in the row; a plurality of plate lines connected to the other of the first and second capacitor electrodes of each of said capacitor elements in said plurality of memory cells; and a plurality of bit lines provided for each column of memory cell array and connected to the other of the source and the drain of each transistor of memory cells included in the column; a plurality of sense amplifiers connected to said bit lines; generating section for generating, from a first supply voltage fed from the outside, a second supply voltage which is lower than said first supply voltage; and supplying section for supplying said first and second electrodes of each capacitor element with said second supply voltage and the ground potential.
In the present invention, a voltage difference between the second supply voltage and the ground potential may be equal to or greater than a coercive voltage of the ferroelectrics of the ferroelectric film.
In the present invention, the voltage difference between the second supply voltage and the ground potential may correspond to a minimum voltage difference with which writing of information to and reading of information from the capacitor element can be achieved.
In the present invention, the generating section may comprise a step-down power supply circuit.
The present invention may comprise, as the supplying section, a plate-line voltage supply circuit, a word-line voltage supply circuit and a sense amplifier drive circuit, wherein the plate-line voltage supply circuit has a function of supplying the plate line with a voltage ranging from the ground potential to the second supply voltage, the word-line voltage supply circuit having a function of supplying each word line with a voltage ranging from the ground potential to a voltage which is at least a threshold voltage of the transistor in each memory cell higher than the second supply voltage and the sense amplifier drive circuit having a function of supplying the sense amplifiers with a voltage ranging from the ground potential to the second supply voltage.
According to the present invention, a supply voltage for the plate-line voltage supply circuit may correspond to a voltage difference between the second supply voltage and the ground potential.
According to the present invention, a supply voltage for the word-line voltage supply circuit may correspond to a voltage difference between the first supply voltage and the ground potential.
According to the present invention, the supply voltage for the word-line voltage supply circuit may correspond to a voltage difference between the second supply voltage and the ground potential.
According to the present invention, a supply voltage for the sense amplifier drive circuit may correspond to a voltage difference between the second supply voltage and the ground potential.
As described above, according to the present invention, the adverse effect that the signal voltage is decreased can be minimized and the permitted number of operation cycles can be increased. Thus, a ferroelectric memory device according to the invention has, amongst others, the advantageous effect that the reliability with respect to the read/write operation can significantly be improved as compared to the conventional ferroelectric memory devices.
The reason why the above advantageous effects can be obtained is that, taking into consideration the fact that the characteristics of the ferroelectrics deteriorate more as the voltage applied to the ferroelectric capacitors increases, the ferroelectric memory device according to the present invention is constructed such that an internal supply voltage, which is lower than the external supply voltage whose value is defined by the requirement of interfacing to the outside, is generated and supplied to the memory cells as their voltage.